Development of a new high-speed data acquisition system prototype for SOI pixel detector using SiTCP-XG, a 10-gigabit Ethernet network processor

We are developing a new readout board with newer generation field-programmable gate array (FPGA) and the 10-gigabit ethernet to improve performance usability of current based on 1-gigabit ethernet. In this board, SiTCP-XG network processor supporting 10 Gigabit Ethernet was implemented. SiTCP is circuit running FPGA, newly developed version that supports Before we constructed prototype system using Xilinx FPGA evaluation KC705 evaluate SiTCP-XG. This tested SOI pixel detector, which has 425,984 (column 832 × row 512 matrix) pixels size 17 μm 2 at synchrotron beamlines PhotonFactory (KEK). first test X-ray imaging for system. The results showed worked stably transfer rate 682 Mbps (equivalent frame 100 fps, limited by detector operation parameters), also 2.4 Gbps 350 maximum performance). These suggest sufficient cover SOIPIX performance.